The invention relates to the field of control loops, and in particular to a control loop to control the on/off timing of differential switches.
Differential switches in which one transistor is turned off while the other is turned on so as to steer a common current along a particular path are used in a number of devices. One such device is a differential current steering digital-to-analog converter (DAC). Generally, a differential current steering DAC is a device that converts a digital value into a differential current by steering an amount of current out one or the other output of a differential output pair depending on the value of each bit in the digital word. When using such differential switches in a differential current steering DAC or other device, it is important to control the on/off timing relationship between the two transistors.
In one aspect, the present invention provides a control loop for controlling the on/off timing relationship between two transistors in a differential switch that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns on while the other is turning off. The control loop comprises a controller and a clock generator. The controller receives an overlap signal indicative of whether the on/off signals are overlapping too much or too little. The overlap signal is derived from the tail node excursion. The clock generator receives a control signal from the controller. The control signal is based on the overlap signal and causes the clock generator to adjust the timing of driver signals used to derive the on/off signals. When more overlap of the on/off signals is needed, the control signal causes the clock generator to adjust the timing of the driver signals such that there is more overlap of the derived on/off signals. When less overlap of the on/off signals is needed, the control signal causes the clock generator to adjust the timing of the driver signals such that there is less overlap of the derived on/off signals.
Another aspect of the present invention provides a method of controlling the on/off timing relationship between two transistors in a differential switch that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns on while the other is turning off. An overlap signal is derived from the tail node excursion. The overlap signal is indicative of whether on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap of the on/off signals is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap of the on/off signals is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.
An alternative way to control the on/off timing relationship between transistors 202 is to adjust the voltage levels of the on/off signals. In this embodiment, the present invention provides a control loop to control the on/off timing relationship between two transistors in a differential switch that are connected at a tail node to a common current generator. The on/off timing relationship of the transistors is controlled by on/off signals that control the state of the transistors such that one transistor turns on while the other is turning off. The control loop comprises a controller and at least one switch driver. The controller receives an overlap signal indicative of whether the on/off timing of the transistors is overlapping too much or too little. The overlap signal is derived from the tail node excursion. The switch driver receives a control signal from the controller, wherein the control signal is based on the overlap signal and causes the switch driver to adjust the voltage of the on/off signals. When more on/off overlap is needed, the control signal causes the switch driver to adjust the voltage of the on/off signals such that there is more overlap of the transistors"" on/off timing. When less on/off overlap is needed, the control signal causes the switch driver to adjust the voltage of the on/off signals such that there is less overlap of the transistors"" on/off timing.
In another aspect of this embodiment, the present invention provides a method of controlling the on/off timing relationship between two transistors in a differential switch that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns on while the other is turning off. An overlap signal is derived from the tail node excursion. The overlap signal is indicative of whether on/off timing is overlapping too much or too little. A control signal is generated based on the overlap signal. The voltage of the on/ff signals is adjusted based on the control signal. When more overlap of the on/off timing is needed, the voltage of the on/off signals is adjusted such that there is more overlap of the transistors"" on/off timing. When less overlap of the on/off timing is needed, the voltage of the on/off signals is adjusted such that there is less overlap of the transistors"" on/off timing.